參數(shù)資料
型號(hào)： 11274-001-XTD
廠商： ON SEMICONDUCTOR
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16
封裝： 0.150 INCH, SOIC-16
文件頁(yè)數(shù)： 3/43頁(yè)
文件大?。?/td> 1343K
代理商： 11274-001-XTD
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
11
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
4.5.1.1 Crystal Loop Lock Status Flag
To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to one, the LOCK/IPRG pin will be low if the
crystal loop becomes unlocked. The flag is always available under software control by reading back the STAT[1] bit, which is
overwritten with the status flag (low = unlocked) in this mode (see Table 6).
4.5.1.2 Out-Of-Range High/Low
The direction the loop has gone out-of-range can be determined by clearing STAT[1] to zero and setting STAT[0] bit to one. If the
CMOS bit is set to one, the LOCK/IPRG pin will go high if the crystal loop went out of range high. If the pin goes to a logic-low, the loop
went out of range low.
The out-of-range information is also available under software control by reading back the STAT[1] bit, which is overwritten by the flag
(high = outof-range high, low = out-of-range low) in this mode. The bit is set or cleared only if the crystal loop loses lock (see Table 6).
4.5.1.3 Crystal Loop Disable
The crystal loop is disabled by setting the XLPDEN bit to a logic-high (1). The bit disables the charge pump circuit in the loop.
Setting the XLPDEN bit low (0) permits the crystal loop to operate as a control loop.
4.6 Connecting the FS6131 to an External Reference Frequency
If a crystal oscillator is not used, tie XIN to ground and shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and FBK pins do not have pull-up or pull-down current, but do have a small amount of hysteresis to reduce the possibility of
extra edges. Signals may be AC-coupled into these inputs with an external DC-bias circuit to generate a DC-bias of 2.5V. Any
reference or feedback signal should be square for best results, and the signals should be rail-to-rail. Unused inputs should be grounded
to avoid unwanted signal injection.
4.7 Differential Output Stage
The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the
program registers (see Table 4).
If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink
current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of IPRG
current to output drive current is shown in Figure 12. Source current is provided by the pull-up resistor that is part of the Thévenin
termination.
0.0
5.0
10.0
15.0
20.0
25.0
0
204060
80
CLKP/CLKN PECL Output Current (mA)
IPRG
Input
Current
(mA)
Figure 12: IPRG to CLKP/CLKN Current
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相關(guān)代理商/技術(shù)參數(shù)
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112740-12 功能描述:RF 連接器 BNC END LAUNCH JACK 16MM HEX .062 PCB RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點(diǎn)電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型:
112740-13 功能描述:RF 連接器 BNC END LAUNCH JACK 14MM HEX .062 PCB RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點(diǎn)電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型:
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