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參數(shù)資料
| 型號： | 11274-001-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 17/43頁 |
| 文件大?。?/td> | 1343K |
| 代理商： | 11274-001-XTP |
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 14: DC Electrical Specifications (Continued)
Parameter
Symbol
Conditions/Description
Min.
Typ.
Max.
Units
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-Level Output Source Current
IOH
VO = 2.4V
-45
-68
mA
Low-Level Output Sink Current
IOL
VO = 0.4V
15
20
mA
zOH
VO = 0.5VDD; output driving high
28
Output Impedance *
zOL
VO = 0.5VDD; output driving low
33
Short Circuit Source Current *
ISCH
VO = 0V; shorted for 30s, max.
-100
mA
Short Circuit Sink Current *
ISCL
VO = 5V; shorted for 30s, max.
100
mA
Clock Outputs, PECL Mode (CLKN, CLKP)
IPRG Current to Output Current Ratio
1:4
Low-Level Output Sink Current
IOL
IPRG input current = 15mA
60
mA
Tristate Output Current
IZ
-10
10
A
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are
± 3σ from typical. Negative currents indicate current
flows out of the device.
Table 15: AC Timing Specifications
Parameter
Symbol
Conditions/Description
Clock
(MHz)
Min.
Typ.
Max.
Units
Overall
CMOS Outputs
130
Output Frequency *
fO(max)
PECL Outputs
230
MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCOSPD = 0
40
160
VCOSPD = 1
40
100
FS6031 Compatible Oscillator (OSCTYPE = 1)
VCOSPD = 0
40
230
VCO Frequency *
fVCO
VCOSPD = 1
40
140
MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCOSPD = 0
125
VCOSPD = 1
75
FS6031 Compatible Oscillator (OSCTYPE = 1)
VCOSPD = 0
130
VCO Gain *
AVCO
VCOSPD = 1
78
MHz/V
LFTC = 0
13.5
Loop Filter Time Constant *
LFTC = 1
135
s
Rise Time *
tr
CMOS Outputs, VO = 0.5V to 4.5V; CL = 15pF
1.1
ns
Fall Time *
tf
CMOS Outputs, VO = 4.5V to 0.5V; CL = 15pF
0.8
ns
Frequency Synthesis
200
s
Lock Time (Main Loop) *
Line Locked Modes (8kHz reference)
10
ms
Disable Time *
From falling edge of SCL for the last data bit
(SHUT = 1 to 0) to output locked
10
s
24
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
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PDF描述 |
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| 11274-502-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-502-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 11274-011 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Line Lock Clock Generator IC |
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