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參數(shù)資料
| 型號(hào)： | 11274-001-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 33/43頁 |
| 文件大?。?/td> | 1343K |
| 代理商： | 11274-001-XTP |
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a
source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is
frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics
system and the graphics system is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively
synchronized to the REF input as shown in Figure 27.
To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input
of the PFD. The reference and feedback dividers are not used.
The output clock frequency is:
total
horizontal
f
HSYNC
CLK
×
=
The only remaining task is to select a post divider modulus (NPx) that allows the VCO frequency to be within its nominal range.
14.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel
clocks generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by
the FS6131 is set to divide the output clock frequency (fCLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.
Video Graphics System
System HSYNC
Clock In
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider (N
F)
Internal
Loop
Filter
R
LF
C
LF
EXTLF
I2C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
FBKDSRC[1:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
CLK)
(f
CLK)
(f
VCO)
R
IPRG
LOCK/
IPRG
Post
Divider
(N
Px)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
CMOS/PECL
Output
CLKN
(f
CLK)
CLKP
C
LP
Figure 27: Block Diagram: Genlocking
39
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
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| 11274-001-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
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| 11274-011 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Line Lock Clock Generator IC |
| 112740-12 | 功能描述:RF 連接器 BNC END LAUNCH JACK 16MM HEX .062 PCB RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點(diǎn)電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型: |
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