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參數(shù)資料
| 型號： | 11274-001-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 1343K |
| 代理商： | 11274-001-XTP |
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
To understand the operation, refer to Figure 3. The M-counter (with a modulus of M) is cascaded with the dual-modulus pre-scaler. If
the prescaler modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN. However, the A-counter
causes the pre-scaler modulus to be altered to N+1 for the first A outputs of the pre-scaler. The A-counter then causes the dual-
modulus prescaler to revert to a modulus of N until the M-counter reaches its terminal state and resets the entire divider. The overall
modulus can be expressed as
)
(
)
1
(
A
M
N
A
+
where M
≥ A, which simplifies to
A
N
M
+
×
4.1.3 Feedback Divider Programming
The requirement that M
≥ A means that the feedback divider can only be programmed for certain values below a divider modulus of 56.
The selection of divider values is listed in Table 2.
If the desired feedback divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program
value. Follow the row to the left to find the M-counter value.
Above a modulus of 56, the feedback divider can be programmed to any value up to 16383. See both Table 3 and Table 8 for additional
programming information.
Table 2: Feedback Modulus Below 56
A-counter: FBKDIV[2:0]
M-Counter:
FBKDIV[13:3]
000
001
010
011
100
101
110
111
00000000001
8
9
-
00000000010
16
17
18
-
00000000011
24
25
26
27
-
00000000100
32
33
34
35
36
-
00000000101
40
41
42
43
44
45
-
00000000110
48
49
50
51
52
53
54
-
00000000111
56
57
58
59
60
61
62
63
Feedback Divider Modulus
4.1.4 Post Divider
The post divider consists of three individually programmable dividers, as shown in Figure 4.
Post
Divider 1
(N
P1)
Post
Divider 2
(N
P2)
Post
Divider 3
(N
P3)
POST3[1:0]
POST2[1:0]
POST1[1:0]
POST DIVIDER (N
Px)
f
out
f
GBL
Figure 4: Post Divider
The moduli of the individual dividers are denoted as NP1, NP2, and NP3, and together they make up the array modulus NPx.
3
2
1
P
Px
N
×
=
4
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
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| 11274-502-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
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