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參數(shù)資料
| 型號： | 11274-001-XTP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-001-XTP |
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22
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 15: AC Timing Specifications (Continued)
Parameter
Symbol
Conditions/Description
Clock (MHz)
Min.
Typ.
Max.
Units
Clock Output (CLKP, CLKN)
Duty cycle*
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
47
54
%
Jitter, long term (
sy(t))
tj(LT)
Rising edges 50ms apart at 2.5V, relative to an ideal clock, CL=15pF,
fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054
mF, RLF=15.7kW,
CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
1.544
270
ps
Rising edges 50ms apart at 2.5V, relative to an ideal clock, CL=15pF,
fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246
mF, RLF=15.7kW,
CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
12.00
160
On rising edges 5ms apart at 2.5V relative to an ideal clock,
CL=15pF, fREF=31.5kHz, NR=1, N=799, NPx=4, CLF=0.015
mF,
RLF=15.7k
W, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7
25.175
100
On rising edges 500
ms apart at 2.5V relative to an ideal clock,
CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2
100
30
On rising edges 500
ms apart at 2.5V relative to an ideal clock,
CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
200
30
Jitter, period (peak-peak)*
tj(
DP)
From rising edge to next rising edge at 2.5V, CL=15pF, fREF=8kHz,
NR=1, NF=193, NPx=64, CLF=0.054
mF, RLF=15.7kW, CLP=1800pF,
OSCTYPE=0, MLCP=3, XLROM=7
1.544
140
ps
From rising edge to next rising edge at 2.5V, CL=15pF, fREF=15kHz,
NR=1, NF=800, NPx=10, CLF=0.0246
mF, RLF=15.7kW, CLP=820pF,
OSCTYPE=0, MLCP=3, XLROM=7
12.00
130
From rising edge to next rising edge at 2.5V, CL=15pF, fREF=31.5kHz,
NR=1, NF=799, NPx=4, CLF=0.015
mF, RLF=15.7kW, CLP=470pF,
OSCTYPE=0, MLCP=3, XLROM=7
25.175
105
From rising edge to next rising edge at 2.5V, CL=15pF, CMOS mode,
fXIN=27MHz, NF=200, NR=27, NPx=2
100
340
From rising edge to next rising edge at 2.5V, CL=15pF, PECL mode,
fXIN=27MHz, NF=200, NR=27, NPx=1
200
270
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not production tested to any specific limits. Min. and Max. characterization data are ± 3
s from typical.
Table 16: Serial Interface Timing Specifications
Parameter
Symbol
Conditions/Description
Standard Mode
Units
Min.
Max.
Clock frequency
fSCL
SCL
0
400
kHz
Bus free time between STOP and START
tBUF
4.7
ms
Setup time, START (repeated)
tsu:STA
4.7
ms
Hold time, START
thd:STA
4.0
ms
Setup time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
ms
Output data valid from clock
tAA
Minimum delay to bridge undefined region of the falling edge of SCL to avoid
unintended START or STOP
3.5
ms
Rise time, data and clock
tR
SDA, SCL
1000
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
4.0
ms
Low time, clock
tLO
SCL
4.7
ms
Setup time, STOP
tsu:STO
4.0
ms
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not production tested to any specific limits. Min. and Max. characterization data are ± 3
s from typical.
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