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參數(shù)資料
| 型號： | 11274-001-XTP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 746K |
| 代理商： | 11274-001-XTP |
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3
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
4.0 Functional Block Description
The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Figure 2, the ML-PLL
consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a
feedback divider, and a post divider.
During operation, the reference frequency (fREF), generated by either the on-board crystal oscillator or an external frequency source, is first reduced
by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as NR for the reference divider.
The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise,
continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback divider (the
modulus is denoted by NF) to close the loop.
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs
of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is
R
REF
F
VCO
N
f
N
f
=
If the VCO frequency is used as the PLL output frequency (fCLK) then the basic PLL equation can be rewritten as
÷÷
è
=
R
F
REF
CLK
N
f
4.1 Main Loop PLL
4.1.1 Reference Divider
The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output) or an
external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and can be
programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.
4.1.2 Feedback Divider
The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully programmable
feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed
between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus
technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider.
For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of
the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-frequency-to-output-
frequency ratio without making both the reference and feedback divider values comparatively large. Large divider moduli are generally undesirable
due to increased phase jitter.
Dual-
Modulus
Prescaler
A
Counter
M
Counter
f
vco
Figure 3: Feedback Divider
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 1127-40-0516 | 制造商:Concord Electronics Inc 功能描述: |
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