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參數(shù)資料
| 型號(hào)： | 11274-502-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大?。?/td> | 1343K |
| 代理商： | 11274-502-XTP |
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 8: Divider Control Bits
Name
Description
REFDIV[11:0]
(Bits 11-0)
REFerence DIVider (NR)
FeedBacK DIVider (NF)
FBKDIV[2:0]
A-Counter Value
FBKDIV[13:0]
(Bits 37-24)
FBKDIV[13:3]
M-Counter Value
POST Divider #1 (NP1)
Bit 17 = 0
Bit 16 = 0
Divide by 1
Bit 17 = 0
Bit 16 = 1
Divide by 2
Bit 17 = 1
Bit 16 = 0
Divide by 4
POST1[1:0]
(Bits 17-16)
Bit 17 = 1
Bit 16 = 1
Divide by 8
POST Divider #2 (NP2)
Bit 19 = 0
Bit 18 = 0
Divide by 1
Bit 19 = 0
Bit 18 = 1
Divide by 3
Bit 19 = 1
Bit 18 = 0
Divide by 5
POST2[1:0]
(Bits 19-18)
Bit 19 = 1
Bit 18 = 1
Divide by 4
POST Divider #3 (NP3)
Bit 21 = 0
Bit 20 = 0
Divide by 1
Bit 21 = 0
Bit 20 = 1
Divide by 3
Bit 21 = 1
Bit 20 = 0
Divide by 5
POST3[1:0]
(Bits 21-20)
Bit 21 = 1
Bit 20 = 1
Divide by 4
Reserved (0)
(Bits 23-22)
Set these reserved bits to 0
19
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 11274-001-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-502-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-502-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-001-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
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