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參數(shù)資料
| 型號(hào)： | 11274-502-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 1343K |
| 代理商： | 11274-502-XTP |
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 15: AC Specifications (Continued)
Parameter
Symbol
Conditions/Description
Clock
(MHz)
Min.
Typ.
Max.
Units
Divider Modulus
Feedback Divider
NF
FBKDIV[13:0] (See also Table 2)
8
16383
Reference Divider
NR
REFDIV[11:0]
1
4095
NP1
POST1[1:0] (See also Table 8)
1
8
NP2
POST2[1:0] (See also Table 8)
1
5
Post Divider
NP3
POST3[1:0] (See also Table 8)
1
5
Clock Output (CLKP, CLKN)
Duty Cycle *
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
47
54
%
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054F,
RLF=15.7k, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
1.544
270
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246F,
RLF=15.7k, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
12.00
160
On rising edges 5ms apart at 2.5V relative to an ideal clock,
CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015F,
RLF=15.7k, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7
25.175
100
On rising edges 500
s apart at 2.5V relative to an ideal clock,
CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2
100
30
Jitter, Long Term (
σ
y(τ)) *
tj(LT)
On rising edges 500
s apart at 2.5V relative to an ideal clock,
CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
200
30
ps
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054F, RLF=15.7k,
CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
1.544
140
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246F, RLF=15.7k,
CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
12.00
130
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015F, RLF=15.7k,
CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7
25.175
105
From rising edge to next rising edge at 2.5V, CL=15pF,
CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2
100
340
Jitter, Period (peak-peak)
*
tj(P)
From rising edge to next rising edge at 2.5V, CL=15pF,
PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
200
270
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data at TA = 27°C and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
Table 16: Serial Interface Timing Specifications
Parameter
Symbol
Conditions/Description
Min.
Max.
Units
Clock frequency
fSCL
SCL
0
400
kHz
Bus free time between STOP and START
tBUF
4.7
s
Set up time, START (repeated)
tsu:STA
4.7
s
Hold time, START
thd:STA
4.0
s
Set up time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
s
Output data valid from clock
tAA
Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP
3.5
s
Rise time, data and clock
tR
SDA, SCL
1000
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
4.0
s
Low time, clock
tLO
SCL
4.7
s
Set up time, STOP
tsu:STO
4.0
s
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are
± 3σ from typical.
25
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
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| 11274-001-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
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| 11274-001-XTD | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 11274-502-XTP | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
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