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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
5.0 I
2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be
controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and
STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the
master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and
a device receiving data as the receiver. I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-
one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable
whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START
or STOP condition. The following bus conditions are defined by the I2C-bus protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-put is high indicates a START condition. All commands to the device must be
preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be
followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START
condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per
data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred
between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is
overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5 Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must
generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the
high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked)
out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
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AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice