參數(shù)資料
型號(hào)： 11274-502-XTP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16
封裝： 0.150 INCH, GREEN, SOIC-16
文件頁(yè)數(shù)： 3/40頁(yè)
文件大?。?/td> 746K
代理商： 11274-502-XTP
11
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
0.0
5 .0
10.0
15 .0
20 .0
25 .0
0
2 0
40
60
80
CLKP/CLKN PECL Output Current (m A)
IPRG
Input
Current
(mA)
Figure 12: IPRG to CLKP/CLKN Current
5.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I
2C-bus specifications except a "general call." The bus has to be controlled
by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while
the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which
mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver.
I
2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while
a logic-zero corresponds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever
the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition.
The following bus conditions are defined by the I
2C-bus protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-put is high indicates a START condition. All commands to the device must be preceded
by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a
STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition
occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit.
相關(guān)PDF資料
PDF描述
11274-001-XTD PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16
11274-001-XTP PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16
11610 BEZEL IEC CONN
116450-01 130MM BLOWER 24 VDC
116521-02 130MM BLOWER 24 VDC
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