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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD835G3V-B-70B81

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

    

    
文件頁(yè)數(shù)：
16/110頁(yè)

    

    
文件大?。?/td>
570K

    

    
代理商：
PSD835G3V-B-70B81


    

    

    

	
    
    
    

    
    
	
    PSD835G2  
    PSD8XX Family
    15
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Periph-
    mode
    *
    *
    FL_data
    Boot_data
    FL_code
    Boot_code
    SR_code
    VM Register
    Bit definitions: 
    Bit 0 0 = PSEN can’t access SRAM in 80C51XA modes.
    1 = PSEN can access SRAM in 80C51XA modes.
    Bit 1 0 = PSEN can’t access Boot in 80C51XA modes.
    1 = PSEN can access Boot in 80C51XA modes.
    Bit 2 0 = PSEN can’t access main Flash in 80C51XA modes.
    1 = PSEN can access main Flash in 80C51XA modes.
    Bit 3 0 = RD can’t access Boot in 80C51XA modes.
    1 = RD can access Boot in 80C51XA modes.
    Bit 4 0 = RD can’t access main Flash in 80C51XA modes.
    1 = RD can access main Flash in 80C51XA modes.
    Bit 7 0 = Peripheral mode of Port F is disabled.
    1 = Peripheral mode of Port F is enabled.
    Note:
     Upon reset, Bit1-Bit4 are loaded to configurations selected by the user in PSDsoft. Bit 0 and Bit 7 are 
    always cleared by reset. Bit 0 to Bit 4 are active only when the device is configured in Philips 80C51XA 
    mode.
    * Not used bit should be set to zero
    8.0
    Register Bit
    Definition
    (cont.)
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    S_size 3
    S_size 2
    S_size 1
    S_size 0
    F_size 3
    F_size 2
    F_size 1
    F_size 0
    Memory_ID0 Register
    Bit definitions: 
    F_size[3:0] = 4h, main Flash size is 2M bit.
    F_size[3:0] = 5h, main Flash size is 8M bit.
    S_size[3:0] = 0h, SRAM size is 0K bit.
    S_size[3:0] = 1h, SRAM size is 16K bit.
    S_size[3:0] = 3h, SRAM size is 64K bit.
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    *
    B_type 1
    B_type 0
    B_size 3
    B_size 2
    B_size 1
    B_size 0
    Memory_ID1 Register
    Bit definitions: 
    B_size[3:0] = 0h, Boot block size is 0K bit.
    B_size[3:0] = 2h, Boot block size is 256K bit.
    B_type[1:0] = 0h, Boot block is Flash memory.
    *
    Not used bit should be set to zero.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD835G3V-B-70B81I
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-B-70J
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-B-70JI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-B-70M
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-B-70MI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD853F2-70J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 70ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD853F2-70M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90JI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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