67
32000D–04/2011
AVR32
The interrupt system requires that an interrupt controller is present outside the core in order to
prioritize requests and generate a correct offset if more than one interrupt source exists for each
priority level. An interrupt controller generating different offsets depending on interrupt request
source is referred to as autovectoring. Note that the interrupt controller should generate
autovector addresses that do not conflict with addresses in use by other events or regular pro-
gram code.
Table 8-1.
Priority and handler addresses for events
Priority
Handler Address
Name
Event source
Stored Return Address
1
0x8000_0000
for AVR32A.
0xA000_0000
for AVR32B.
Reset
External input
Undefined
2
Provided by OCD system
OCD Stop CPU
OCD system
First non-completed instruction
3
EVBA+0x00
Unrecoverable exception
Internal
PC of offending instruction
4
EVBA+0x04
TLB multiple hit
Internal signal
PC of offending instruction
5
EVBA+0x08
Bus error data fetch
Data bus
First non-completed instruction
6
EVBA+0x0C
Bus error instruction fetch
Data bus
First non-completed instruction
7
EVBA+0x10
NMI
External input
First non-completed instruction
8
Autovectored
Interrupt 3 request
External input
First non-completed instruction
9
Autovectored
Interrupt 2 request
External input
First non-completed instruction
10
Autovectored
Interrupt 1 request
External input
First non-completed instruction
11
Autovectored
Interrupt 0 request
External input
First non-completed instruction
12
EVBA+0x14
Instruction Address
ITLB
PC of offending instruction
13
EVBA+0x50
ITLB Miss
ITLB
PC of offending instruction
14
EVBA+0x18
ITLB Protection
ITLB
PC of offending instruction
15
EVBA+0x1C
Breakpoint
OCD system
First non-completed instruction
16
EVBA+0x20
Illegal Opcode
Instruction
PC of offending instruction
17
EVBA+0x24
Unimplemented instruction
Instruction
PC of offending instruction
18
EVBA+0x28
Privilege violation
Instruction
PC of offending instruction
19
EVBA+0x2C
Floating-point
FP Hardware
PC of offending instruction
20
EVBA+0x30
Coprocessor absent
Instruction
PC of offending instruction
21
EVBA+0x100
Supervisor call
Instruction
PC(Supervisor Call) +2
22
EVBA+0x34
Data Address (Read)
DTLB
PC of offending instruction
23
EVBA+0x38
Data Address (Write)
DTLB
PC of offending instruction
24
EVBA+0x60
DTLB Miss (Read)
DTLB
PC of offending instruction
25
EVBA+0x70
DTLB Miss (Write)
DTLB
PC of offending instruction
26
EVBA+0x3C
DTLB Protection (Read)
DTLB
PC of offending instruction
27
EVBA+0x40
DTLB Protection (Write)
DTLB
PC of offending instruction
28
EVBA+0x44
DTLB Modified
DTLB
PC of offending instruction