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參數(shù)資料
| 型號： | 843004AG-01LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 170 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封裝： | 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 683K |
| 代理商： | 843004AG-01LF |
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
9
ICS843004-01 REV B JUNE 30, 2006
ICS843004-01
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure X. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
applications, R1
and R2 can be 100
. This can also be accomplished by removing
R1 and making R2 50
.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
TERMINATION FOR 3.3V LVPECL OUTPUT
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating fre-
quency and minimize signal distor tion.
Figures 4A and 4B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 843004AG-01LFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 843004AG-01T | 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ SYNTHESIZER SGL 24TSSOP - Tape and Reel |
| 843004AG-02 | 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ SYNTHESIZER SGL 24TSSOP - Rail/Tube |
| 843004AG-02LF | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Synthesizer Single 24-Pin TSSOP Tube 制造商:IDT from Components Direct 功能描述:IDT 843004AG-02LF PLL - Rail/Tube 制造商:IDT 功能描述:IDT 843004AG-02LF PLL |
| 843004AG-02LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Synthesizer Single 24-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ SYNTHESIZER SGL 24TSSOP - Tape and Reel |
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