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參數(shù)資料
| 型號： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁數(shù)： | 76/120頁 |
| 文件大?。?/td> | 447K |
| 代理商： | 91C94 |
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59
Status Register (EPHSR), and enabling of these
sources can be done via the Control Register.
The possible sources are:
LINK_OK transition.
CTR_ROL - Statistics counter roll over.
TXENA cleared - A fatal transmit error occurred
forcing TXENA to be cleared. TX_SUC will be
low and the specific reason will be reflected by
the bits:
TXUNRN - Transmit underrun
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
RX_OVRN INT - Set when the receiver overruns
due to a failed memory allocation or when a
packet exceeding 1536 bytes is received, or
when a packet reception is stopped on-the-fly by
setting the RCV_DISCRD bit in the ERCV
register. The RX_OVRN bit of the EPHSR will
also be briefly set. The RX_OVRN INT bit,
however, latches the overrun condition for the
purpose of being polled or generating an
interrupt, and will only be cleared by writing the
acknowledge register with the RX_OVRN INT bit
set.
ALLOC INT - Set when an MMU request for TX
pages allocation is completed.
This bit is the
complement
of
the
FAILED
bit
in
the
ALLOCATION RESULT register. The ALLOC
INT ENABLE bit should only be set following an
allocation command, and cleared upon servicing
the interrupt.
TX EMPTY INT - Set if the TX FIFO goes
empty, can be used to generate a single
interrupt at the end of a sequence of packets
enqueued for transmission. This bit latches the
empty condition, and the bit will stay set until it
is
specifically
cleared
by
writing
the
acknowledge register with the TX EMPTY INT
bit set. If a real time reading of the FIFO empty
is desired, the bit should be first cleared and
then read.
The TX EMPTY INT ENABLE should only be set
after the following steps:
a)
A packet is enqueued for transmission
b)
The previous empty condition is cleared
(acknowledged).
TX INT - Set when at least one packet
transmission was completed. The first packet
number to be serviced can be read from the
FIFO PORTS register. The TX INT bit is always
the logic complement of the TEMPTY bit in the
FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by
writing the Interrupt Acknowledge Register with
the TX INT bit set.
RCV INT - Set when a receive interrupt is
generated. The first packet number to be
serviced can be read from the FIFO PORTS
register. The RCV INT bit is always the logic
complement of the REMPTY bit in the FIFO
PORTS register.
ERCV
INT
-
Early
receive
interrupt.
Set
whenever a receive packet is being received,
and the number of bytes received into memory
exceeds
the
value
programmed
as
ERCV
THRESHOLD (Bank 3, Offset Ch). ERCV INT
stays set until acknowledged by writing the
INTERRUPT ACKNOWLEDGE REGISTER with
the ERCV INT bit set.
Note: If the driver uses AUTO RELEASE mode
it should enable TX EMPTY INT as well as TX
INT. TX EMPTY INT will be set when the
complete sequence of packets is transmitted.
TX INT will be set if the sequence stops due to a
fatal error on any of the packets in the
sequence.
Note: For edge triggered systems, the Interrupt
Service Routine should clear the Interrupt Mask
Register,
and
only
enable
the
appropriate
interrupts after the interrupt source is serviced
(acknowledged).
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