參數(shù)資料
型號(hào)： ADSP-21488KSWZ-3B
廠商： Analog Devices Inc
文件頁數(shù)： 15/68頁
文件大小： 0K
描述： IC CCD SIGNAL PROCESSOR 176LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 350MHz
非易失內(nèi)存： 外部
芯片上RAM： 3Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 176-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 176-LQFP-EP（24x24）
包裝： 托盤
Rev. B
|
Page 22 of 68
|
March 2013
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 43 on Page 55 for voltage reference levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, the processor core,
and the serial ports. During reset, program the ratio between the
processor’s internal clock frequency and external (CLKIN)
clock frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 4). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator (VCO)
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 20.
The product of CLKIN and PLLM must never exceed 1/2 of
fVCO (max) in Table 20 if the input divider is not enabled
(INDIV = 0).
The product of CLKIN and PLLM must never exceed fVCO
(max) in Table 20 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) ÷ PLLD
where:
fVCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 2, 4, 8, or 16 based on the divider value programmed on
the PMCTL register. During reset this value is 2.
fINPUT = is the input frequency to the PLL.
fINPUT = CLKIN when the input divider is disabled or
fINPUT = CLKIN ÷ 2 when the input divider is enabled
Figure 4. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
SDRAM
DIVIDER
BYPASS
MUX
PMCTL
(SDCKR)
CCLK
PLL
XTAL
CLKIN
DIVIDER
RESET
f
VCO ÷ (2 × PLLM)
BUF
VCO
BUF
PMCTL
(INDIV)
PLL
DIVIDER
RESETOUT
CLKOUT (TEST ONLY)*
DELAY OF
4096 CLKIN
CYCLES
PCLK
PMCTL
(PLLBP)
PMCTL
(PLLD)
f
VCO
f
CCLK
fINPUT
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f
INPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
CLK_CFGx/
PMCTL (2 × PLLM)
DIVIDE
BY 2
PIN
MUX
PMCTL
(PLLBP)
CCLK
RESETOUT
CORESRST
SDCLK
BYPASS
MUX
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