參數(shù)資料
型號(hào): PIC16LCE624-04E/P
廠商: Microchip Technology
文件頁(yè)數(shù): 14/100頁(yè)
文件大?。?/td> 0K
描述: IC MCU CMOS 1K OTP W/EEPRM 18DIP
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: OTP
EEPROM 大?。?/td> 128 x 8
RAM 容量: 96 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
ENC424J600/624J600
DS39935C-page 110
2010 Microchip Technology Inc.
When LINKIF link status change interrupt flag is set, it
means auto-negotiation or parallel detection is
complete. Once auto-negotiation is complete, the MAC
registers related to Duplex mode must be reconfigured.
Determine the new Duplex mode by reading the
PHYDPX bit (ESTAT<10>). Once this is done, update
the MACON2, MACLCON, MAIPG and MABBIPG
registers as described in Section 8.9 “After Link
.
REGISTER 12-1:
PHCON1: PHY CONTROL REGISTER 1
R/W-0
R/W-1
R/W-0
PRST
PLOOPBK
SPD100(1)
ANEN
PSLEEP
r
RENEG
PFULDPX(1)
bit 15
bit 8
R/W-0
R-0
r
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PRST:
PHY Reset bit
1
= Perform PHY Reset. Hardware automatically clears this bit to ‘0’ when the Reset is complete.
0
= PHY is not in Reset (normal operation)
bit 14
PLOOPBK:
PHY Loopback Enable bit
1
= Loopback is enabled
0
= Normal operation
bit 13
SPD100:
PHY Speed Select Control bit(1)
1
= 100 Mbps
0
= 10 Mbps
bit 12
ANEN:
PHY Auto-Negotiation Enable bit
1
= Auto-negotiation is enabled. SPD100 and PFULDPX are ignored.
0
= Auto-negotiation is disabled. SPD100 and PFULDPX control the operating speed and duplex.
bit 11
PSLEEP:
PHY Sleep Enable bit
1
= PHY is powered down
0
= Normal operation
bit 10
Reserved:
Write as ‘0’, ignore on read
bit 9
RENEG:
Restart Auto-Negotiation Control bit
1
= Restart the auto-negotiation process. Hardware automatically clears this bit to ‘0’ when the
auto-negotiation process starts.
0
= Normal operation
bit 8
PFULDPX:
PHY Duplex Select Control bit(1)
1
= Full duplex
0
= Half duplex
bit 7
Reserved:
Write as ‘0’, ignore on read
bit 6-0
Reserved:
Ignore on read
Note 1:
Applicable only when auto-negotiation is disabled (ANEN = 0).
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