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| 型號： | MC68EC000AA10 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 10MHZ 64-QFP |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 10MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-QFP |
| 供應(yīng)商設(shè)備封裝： | 64-QFP（14x14） |
| 包裝： | 托盤 |
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13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
Applies to 3.3V and 5V.
NOTES: 1.
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
Actual value depends on clock period.
3.
If #47 is satised for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
5.
If the asynchronous input setup time (#47) requirement is satised for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6.
When AS and R/W are equally loaded (
±20%), subtract 5 ns from the values given in these columns.
7.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
NUM
CHARACTERISTIC
10MHz
16MHz
20MHz
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
29
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
0—0—0—
ns
29A
AS, LDS, UDS Negated to Data-In High Impedance (Read)
—
150
—
90
—
75
ns
30
AS, LDS, UDS Negated to BERR Negated
0—0—0—
ns
312,5
DTACK Asserted to Data-In Valid (Setup Time on Read)
—
65
—
50
—
42
ns
32
HALT and RESET Input Transition Time
0
150
0
150
0
150
ns
33
Clock High to BG Asserted
—
35
—
30
—
25
ns
34
Clock High to BG Negated
—
35
—
30
—
25
ns
35
BR Asserted to BG Asserted
1.5
3.5
1.5
3.5
1.5
3.5
Clks
367
BR Negated to BG Negated
1.5
3.5
1.5
3.5
1.5
3.5
Clks
38
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
—55—50—42
ns
39
BG Width Negated
1.5
—
1.5
—
1.5
—
Clks
44
AS, LDS, UDS Negated to AVEC Negated
0
55
0
50
0
42
ns
475
Asynchronous Input Setup Time
5—5—5—
ns
482,3
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
52
Data-In Hold from Clock High
0—0—0—
ns
53
Data-Out Hold from Clock High (Write)
0—0—0—
ns
55
R/W Asserted to Data Bus Impedance Change (Write)
20
—
10
—
0
—
ns
564
HALT, RESET Pulse Width
10
—
10
—
10
—
Clks
587
BR Negated to AS, LDS, UDS, R/W Driven
1.5
—
1.5
—
1.5
—
Clks
58A7
BR Negated to FC Driven
1—1—1—
Clks
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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