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參數資料
| 型號： | PIC24FJ16GA002-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數： | 20/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 16K 28-SSOP |
| 產品培訓模塊： | Graphics LCD System and PIC24 Interface Asynchronous Stimulus |
| 特色產品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 標準包裝： | 47 |
| 系列： | PIC® 24F |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，PMP，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，LVD，POR，PWM，WDT |
| 輸入/輸出數： | 21 |
| 程序存儲器容量： | 16KB（5.5K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數據轉換器： | A/D 10x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 產品目錄頁面： | 647 (CN2011-ZH PDF) |
| 配用： | DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28 AC164338-ND - MOD SKT PIC24F/DSPIC33F 28SOIC DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 |
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2008 Microchip Technology Inc.
DS39768D-page 27
PIC24FJXXXGA0XX
4.0
DEVICE PROGRAMMING –
ENHANCED ICSP
This section discusses programming the device
through Enhanced ICSP and the programming execu-
tive. The programming executive resides in executive
memory (separate from code memory) and is executed
when Enhanced ICSP Programming mode is entered.
The programming executive provides the mechanism
for the programmer (host device) to program and verify
the PIC24FJXXXGA0XX devices using a simple
command set and communication protocol. There are
several basic functions provided by the programming
executive:
Read Memory
Erase Memory
Program Memory
Blank Check
Read Executive Firmware Revision
The programming executive performs the low-level
tasks required for erasing, programming and verifying
a device. This allows the programmer to program the
device by issuing the appropriate commands and data.
Table 4-1 summarizes the commands. A detailed
description
for
each
command
is
provided
in
TABLE 4-1:
COMMAND SET SUMMARY
The programming executive uses the device’s data
RAM for variable storage and program execution. After
the programming executive has run, no assumptions
should be made about the contents of data RAM.
4.1
Overview of the Programming
Process
Figure 4-1 shows the high-level overview of the
programming process. After entering Enhanced ICSP
mode, the programming executive is verified. Next, the
device
is
erased.
Then,
the
code
memory
is
programmed, followed by the configuration locations.
Code memory (including the Configuration registers) is
then verified to ensure that programming was successful.
After the programming executive has been verified
in memory
(or
loaded
if
not
present),
the
PIC24FJXXXGA0XX family can be programmed using
the command set shown in Table 4-1.
FIGURE 4-1:
HIGH-LEVEL ENHANCED
ICSP PROGRAMMING FLOW
4.2
Confirming the Presence of the
Programming Executive
Before programming can begin, the programmer must
confirm that the programming executive is stored in
executive memory. The procedure for this task is
shown in Figure 4-2.
First, In-Circuit Serial Programming mode (ICSP) is
entered. Then, the unique Application ID Word stored in
executive memory is read. If the programming executive
is resident, the Application ID Word is BBh, which means
programming can resume as normal. However, if the
Application ID Word is not BBh, the programming
executive must be programmed to executive code
memory using the method described in Section 5.4
Section 3.0 “Device Programming – ICSP” describes
the ICSP programming method. Section 3.11 “Reading
the Application ID Word” describes the procedure for
reading the Application ID Word in ICSP mode.
Command
Description
SCHECK
Sanity Check
READC
Read Device ID Registers
READP
Read Code Memory
PROGP
Program One Row of Code Memory
and Verify
PROGW
Program One Word of Code Memory
and Verify
QBLANK
Query if the Code Memory is Blank
QVER
Query the Software Version
Start
Done
Perform Chip
Erase
Program Memory
Verify Program
Enter Enhanced ICSP
Program Configuration Bits
Verify Configuration Bits
Exit Enhanced ICSP
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