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參數(shù)資料
| 型號(hào)： | ADCLK950/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADCLK950 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SIGe |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘緩沖器 / 驅(qū)動(dòng)器 / 接收器 / 變換器 |
| 已用 IC / 零件： | ADCLK950 |
| 主要屬性： | 2 個(gè)可選輸入，10 輸出 |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
ADCLK950
Rev. A | Page 10 of 12
CLOCK INPUT SELECT (IN_SEL) SETTINGS
A Logic 0 on the IN_SEL pin selects the Input CLK0 and
Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1
and Input CLK1.
PCB LAYOUT CONSIDERATIONS
The ADCLK950 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important
to use low impedance supply planes for both the negative supply
(VEE) and the positive supply (VCC) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
The following references to the GND plane assume that the VEE
power plane is grounded for LVPECL operation. Note that for
ECL operation, the VCC power plane becomes the ground plane.
It is also important to adequately bypass the input and output
supplies. Place a 1 μF electrolytic bypass capacitor within several
inches of each VCC power supply pin to the GND plane. In
addition, place multiple high quality 0.001 μF bypass capacitors
as close as possible to each of the VCC supply pins, and connect
the capacitors to the GND plane with redundant vias. Carefully
select high frequency bypass capacitors for minimum induc-
tance and ESR. To improve the effectiveness of the bypass at
high frequencies, minimize parasitic layout inductance. Also,
avoid discontinuities along input and output transmission lines
that can affect jitter performance.
In a 50 Ω environment, input and output matching have a
significant impact on performance. The buffer provides internal
50 Ω termination resistors for both CLKx and CLKx inputs.
Normally, the return side is connected to the reference pin that is
provided. Carefully bypass the termination potential using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If the inputs are dc-coupled to a source, take care to
ensure that the pins are within the rated input differential and
common-mode ranges.
If the return is floated, the device exhibits a 100 Ω cross termi-
nation, but the source must then control the common-mode
voltage and supply the input bias currents.
There are ESD/clamp diodes between the input pins to prevent
the application from developing excessive offsets to the input
transistors. ESD diodes are not optimized for best ac perfor-
mance. When a clamp is required, it is recommended that
appropriate external diodes be used.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK950 package is both
an electrical connection and a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to the VEE power plane.
When properly mounted, the ADCLK950 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK950. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
The ADCLK950 evaluation board (ADCLK950/PCBZ) provides
an example of how to attach the part to the PCB.
VIAS TO VEE POWER
PLANE
08
27
9-
01
8
Figure 18. PCB Land for Attaching Exposed Paddle
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