參數(shù)資料
型號(hào)： ADSP-21160N
廠商： Analog Devices, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述： 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁數(shù)： 26/53頁
文件大?。?/td> 1680K
代理商： ADSP-21160N
PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
26
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asyn-
chronous access mode. Note that timing for ACK, DATA,
RDx
,
WRx
, and
DMAG
strobe timing parameters only applies
to asynchronous access mode.
Table 11. Memory Write—Bus Master
Parameter
Timing Requirements:
t
DAAK
t
DSAK
t
SAKC
t
HAKC
Switching Characteristics:
t
DAWH
Min
Max
Unit
ACK Delay from Address, Selects
1,2
ACK Delay from
WRx
Low
1,3
ACK Setup to CLKIN
1,3
ACK Hold After CLKIN
1,3
1
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or t
SAKC
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
2
The falling edge of
MSx
,
BMS
is referenced.
3
Note that timing for ACK, DATA,
RDx
,
WRx
, and
DMAG
strobe timing parameters only applies to asynchronous access mode.
4
See
Example System Hold Time Calculation on page 47
for calculation of hold times given capacitive and dc loads.
t
CK
–0.5t
CCLK
–12+W
t
CK
–0.75t
CCLK
–11+W
ns
ns
ns
ns
0.5t
CCLK
+3
1
Address,
CIF
, Selects to
WRx
Deasserted
2,3
Address,
CIF
, Selects to
WRx
Low
2
WRx
Pulse width
3
Data Setup before
WRx
High
3
Address Hold after
WRx
Deasserted
3
Data Hold after
WRx
Deasserted
3
Data Disable after
WRx
Deasserted
3,4
WRx
High to
WRx
,
RDx
,
DMAGx
Low
3
Data Disable before
WRx
or
RDx
Low
WRx
Low to Data Enabled
W = (number of wait states specified in WAIT register) × t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
t
CK
–0.25t
CCLK
–3+W
ns
t
DAWL
t
WW
t
DDWH
t
DWHA
t
DWHD
t
DATRWH
t
WWR
t
DDWR
t
WDE
0.25t
CCLK
–3
t
CK
–0.5t
CCLK
–1+W
t
CK
–0.5t
CCLK
–1+W
0.25t
CCLK
–1+H
0.25t
CCLK
–1+H
0.25t
CCLK
–2+H
0.5t
CCLK
–1+HI
0.25t
CCLK
–1+I
–0.25t
CCLK
–1
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.25t
CCLK
+2+H
Figure 18. Memory Write—Bus Master
t
DATRWH
RDx
DMAG
ACK
DATA
WRx
ADDRESS
MSx
,
BMS
,
CIF
t
DAWL
t
WW
t
DAAK
t
WWR
t
WDE
t
DDWR
t
DWHA
t
DAWH
t
DSAK
t
DDWH
t
DWHD
t
SAKC
t
HAKC
CLKIN
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