參數(shù)資料
型號(hào)： BT865AKPF
英文描述： Color Encoder Circuit
中文描述： 顏色編碼器電路
文件頁(yè)數(shù)： 16/76頁(yè)
文件大?。?/td> 1050K
代理商： BT865AKPF
1.0 Circuit Description
Bt864A/865A
1.4 HSYNC* Timing
YCrCb to NTSC/PAL Digital Video Encoder
1-6
Conexant
100138B
1.4 HSYNC* Timing
1.4.1 Master Mode
There are two HSYNC* timing modes in master mode; default mode and variable
HSYNC* timing mode. The variable HSYNC* timing mode is enabled by setting
ADJHSYNC high. This mode allows the user to specify the placement of the
falling and rising edges of HSYNC* by using the HSYNCF and HSYNCR
registers, respectively. The values of registers HSYNCF and HSYNCR
correspond to the pixel count of the internal pixel counter (see
Figure 1-3
).
HSYNCF and HSYNCR cannot be zero and cannot be equal. Values must also be
less than or equal to the total horizontal resolution given in
Table 1-2
. If the
internal pixel counter resets before the rising edge occurs, the part will not
automatically reset, but will wait until the pixel counter reaches the specified
HSYNCR value. The placement of the analog horizontal sync pulse is fixed
relative to the internal pixel counter, therefore when the rising and falling edges of
HSYNC* are moved, the pipeline delay between the HSYNC* pulse and the
analog horizontal sync pulse is altered. In this mode, the pipeline delay from
HSYNC* to analog sync out is 40–(2*HSYNCF) if SYNCDLY = 0, and
41–(2*HSYNCF) if SYNCDLY = 1. In the default HSYNC* timing mode, the
placement of the edges of the HSYNC* pulse are fixed, with the exception of the
one clock delay available through the register SYNCDLY. In this mode, the
pipeline delay from HSYNC* to analog sync out is 40 clocks if SYNCDLY = 0,
and 41 clocks if SYNCDLY = 1. In the default mode, the delay from internal
horizontal pixel counter reset to the falling edge of HSYNC* is 2 clocks.
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