參數(shù)資料
型號(hào)： CS8140YDWR24
廠(chǎng)商： ZF Electronics Corporation
英文描述： T1/E1 Transformer w/Surge Protect
中文描述： 5V的，500mA的線(xiàn)性穩(wěn)壓器具有使能，以及看門(mén)狗復(fù)位
文件頁(yè)數(shù)： 8/12頁(yè)
文件大小： 214K
代理商： CS8140YDWR24
8
C
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, V
OUT
will be at 5V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent cur-
rent of 250μA.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
lead (Figure 3) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of C
DELAY
. The lim-
its are determined according to the following equations for
the CS8140:
(a)
t
WDILOWER
= (1.3 x 10
5
)C
DELAY
or
f
WDI(LOWER)
= (7.69 x 10
-6
)C
DELAY-1
(b)
t
WDI(UPPER)
= (3.82 x 10
-4
)C
DELAY
or
f
WDI(UPPER)
= (2.62 x 10
-5
)C
DELAY-1
For the CS8141 the lower limit is determined by the equa-
tions in (a) above.
The capacitor C
DELAY
also determines the frequency of the
signal and the POWER-ON-
period.
RESET
(POR) delay
Function
The
nal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when V
OUT
drops below V
OUT
-4.5% for more than 2μs (Figure 4b.)
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the
correct Watchdog input signal reappears at the lead. The
duration of the
pulse is determined by C
DELAY
according to the following equation:
function is activated when the Watchdog sig-
lead (Figure 3) until the
t
WDI(
)
= (1 x10
4
)C
DELAY
RESET
4a: Power
and Power Down
4b: Undervoltage Triggered
If an undervoltage condition exists, the voltage on the
lead goes low and the delay capacitor, C
DELAY
, is
discharged.
remains low until output is in regula-
tion, the voltage on C
DELAY
exceeds the upper switching
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
t
POR(typ)
= (4.75 x 10
5
) C
DELAY
The
external cap C
DELAY
.
The output of the reset circuit is an open collector NPN.
is operational down to V
OUT
= 1V. Both
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
delay circuit is also programmed with the
and
RESET
RESET
RESET
RESET
RESET
RESET
V
OUT
V
OUT
-4.5%
<2
m
S
RESET
5V
t
POR
3
2
m
s
RESET
V
OUT
V
R
HI
V
R
LO
V
R
LO
t
POR
RESET
V
R
PEAK
RESET Circuit Waveforms with Delays Indicated
RESET
RESET
RESET
RESET
RESET
RESET
Circuit Description: continued
Application Notes
The CS8140 with its unique integration of linear regulator
and control features:
, ENABLE and WATCHDOG,
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog fre-
quency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
The reset delay is given by:
t
POR(typ)
= (4.75
x
10
5
)C
DELAY
Assume that the reset delay must be 200ms minimum.
From the CS8140 data sheet the reset delay has a ±37% tol-
erance due to the regulator.
Assume the capacitor tolerance is ±10%.
t
POR
(min) = (4.75 x 10
5
x 0.63) x C
DELAY
x 0.9
C
DELAY
(min) =
C
DELAY
= (min) = 0.743 μF
Closest standard value is 0.82μF.
Minimum and maximum delays using 0.82μF are 220ms
and 586ms.
t
POR
(min)
2.69 x 10
5
RESET
CS8140 Design Example
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8140YN14 功能描述:IC REG LDO 5V .5A 14DIP RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線(xiàn)性 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式和可調(diào)式 輸出電壓:3.3V，1.25 V ~ 5.7 V 輸入電壓:4.5 V ~ 7 V 電壓 - 壓降（標(biāo)準(zhǔn)）:1.1V @ 1A 穩(wěn)壓器數(shù)量:2 電流 - 輸出:1A 電流 - 限制（最?。?1A 工作溫度:0°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:TO-252-5，DPak（4 引線(xiàn) + 接片），TO-252AD 供應(yīng)商設(shè)備封裝:PPAK 包裝:管件 其它名稱(chēng):497-3576-5
CS8140YT7 功能描述:IC REG LDO 5V .5A TO220-7 RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線(xiàn)性 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式和可調(diào)式 輸出電壓:3.3V，1.25 V ~ 5.7 V 輸入電壓:4.5 V ~ 7 V 電壓 - 壓降（標(biāo)準(zhǔn)）:1.1V @ 1A 穩(wěn)壓器數(shù)量:2 電流 - 輸出:1A 電流 - 限制（最?。?1A 工作溫度:0°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:TO-252-5，DPak（4 引線(xiàn) + 接片），TO-252AD 供應(yīng)商設(shè)備封裝:PPAK 包裝:管件 其它名稱(chēng):497-3576-5
CS8140YTHA7 功能描述:IC REG LDO 5V .5A TO220-7 RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線(xiàn)性 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式和可調(diào)式 輸出電壓:3.3V，1.25 V ~ 5.7 V 輸入電壓:4.5 V ~ 7 V 電壓 - 壓降（標(biāo)準(zhǔn)）:1.1V @ 1A 穩(wěn)壓器數(shù)量:2 電流 - 輸出:1A 電流 - 限制（最?。?1A 工作溫度:0°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:TO-252-5，DPak（4 引線(xiàn) + 接片），TO-252AD 供應(yīng)商設(shè)備封裝:PPAK 包裝:管件 其它名稱(chēng):497-3576-5
CS8140YTVA7 功能描述:IC REG LDO 5V .5A TO220-7 RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線(xiàn)性 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式和可調(diào)式 輸出電壓:3.3V，1.25 V ~ 5.7 V 輸入電壓:4.5 V ~ 7 V 電壓 - 壓降（標(biāo)準(zhǔn)）:1.1V @ 1A 穩(wěn)壓器數(shù)量:2 電流 - 輸出:1A 電流 - 限制（最?。?1A 工作溫度:0°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:TO-252-5，DPak（4 引線(xiàn) + 接片），TO-252AD 供應(yīng)商設(shè)備封裝:PPAK 包裝:管件 其它名稱(chēng):497-3576-5
CS8141 制造商:CHERRY 制造商全稱(chēng):CHERRY 功能描述:5V, 500mA Linear Regulator with ENABLE, , and Watchdog RESET
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