參數(shù)資料
型號: CXA1616N
廠商: NXP Semiconductors N.V.
英文描述: Switched-Capacitor Voltage Converters With Regulator 8-PDIP 0 to 70
中文描述: 同步鑒別用于CRT顯示
文件頁數(shù): 4/20頁
文件大?。?/td> 496K
代理商: CXA1616N
– 4 –
CXA1616N/S
V
CC
20k
12k
16k
200
8k
6
1k
1k
3.8V
30μA
Pin No.
SSOP
SDIP
Symbol
EHC
VIDEO IN
HD SEL
TIMING
3.0, 4.8V
4.5V
10.5V
6
7
8
9
6
7
8
9
Equivalent circuit
Description
Connects a quasi-peak hold circuit
with a 33k
resistance and 0.22μF
capacitor to discriminate input signal
existence during composite sync input.
When there is a composite sync, the
voltage is held by the quasi-peak hold
circuit at 4.2 to 4.8V. This voltage is
then compared to a 3.8V reference
voltage, and an input signal is judged
to exist.
The voltage is 3.0V when no input
signal exists.
Inputs the sync-on video (sync is
negative polarity). Connect a 0.47μF
capacitor and a 270
resistance in
series between the pin and its signal
source.
The slice level is determined by the
relationship between the sync
frequency and Pulse width and the
sum of the 200
internal resistance
and the 270
external resistance
multiplied by the 29μA current.
V
29μA
×
(T
2
/T
1
)
×
(200 + 270)
Selects whether or not to output the
VD interval portion of HD (H Drive
Pulse).
Input is at TTL Ievel.
V Low
0.5V
V High
2.0V
Low level: The VD interval HD is not
output.
High level or open: The VD interval HD
is output as is.
Connect a desired capacitor and a
12k
resistance in parallel to GND.
This capacitor changes the output
pulse width of clamp pulse.
(See Fig. 1)
Pin voltage
200
V
CC
4k
29μA
72k
7
8.3V
5.8V
16k
T
2
T
1
V
200k
1k
4.5V
8
70k
9
V
CC
10k
17k
1k
30μA
100
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