參數(shù)資料
型號(hào)： CY3950V484-125BBI
廠商： Cypress Semiconductor Corp.
英文描述： CPLDs at FPGA Densities
中文描述： CPLD器件在FPGA的密度
文件頁數(shù)： 41/86頁
文件大小： 1212K
代理商： CY3950V484-125BBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 46 of 86
Reconfig
Input
Pin to start configuration of Delta39K
TCLK
Input
JTAG Test Clock
TDI
Input
JTAG Test Data In
TDO
Output
JTAG Test Data Out
TMS
Input
JTAG Test Mode Select
VCC
Power
Operating Voltage
VCCIO0
Power
VCC for I/O bank 0
VCCIO1
Power
VCC for I/O bank 1
VCCIO2
Power
VCC for I/O bank 2
VCCIO3
Power
VCC for I/O bank 3
VCCIO4
Power
VCC for I/O bank 4
VCCIO5
Power
VCC for I/O bank 5
VCCIO6
Power
VCC for I/O bank 6
VCCIO7
Power
VCC for I/O bank 7
VCCJTAG
Power
VCC for JTAG pins
VCCCNFG
Power
VCC for Configuration port
VCCPLL
[18]
Power
VCC for PLL
VCCPRG
Power
VCC for programming the Self-Boot solution embedded boot PROM
Config_Done
Output
Flag indicating that configuration is complete
CCLK
Output
Configuration Clock for serial interface with the external boot PROM
CCE
Output
Chip select for the external boot PROM (active low)
Data
Input
Pin to receive configuration data from the external boot PROM
Reset
Output
Reset signal to interface with the external boot PROM
Table 8. Pin Definition Table
Pin Name
Function
Description
Table 9. Mode Select (MSEL) Pin Connectivity Table
GND
Delta39K - Self-Boot Solution
VCCCNFG
Delta39K - with external boot PROM
Table 10. I/O Banks for Global Clock and Global Control
Pins (in all densities and packages)
GCLK[0]
GCTL[0]
GCLK[1]
GCTL[1]
GCLK[2]
GCTL[2]
GCLK[3]
GCTL[3]
Bank
Number
05
67
Table 11. 208 EQFP/PQFP Pin Table
Pin
CY39030
CY39050
CY39100
CY39165
CY39200
1
GCTL0
2
GND
3
GCLK0
4
GND
5
IO0
6
IO0
7
IO0
8IO/VREF0
IO/VREF0
9
IO0
10
IO0
11
VCCIO0
Note:
18. The PLL is available in Delta39K ‘V’ devices (2.5V/3.3V) and not in Delta39K ‘Z’ devices (1.8V). In Delta39K ‘Z’ devices, connect VCCPLL to VCC.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY3950V484-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950V484-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950V484-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950V484-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950Z208-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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