參數(shù)資料
型號(hào)： CY3950V484-125MBI
廠商： Cypress Semiconductor Corp.
英文描述： CPLDs at FPGA Densities
中文描述： CPLD器件在FPGA的密度
文件頁數(shù)： 23/86頁
文件大?。?/td> 1212K
代理商： CY3950V484-125MBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 3 of 86
General Description
The Delta39K family, based on a 0.18-mm, six-layer metal
CMOS logic process, offers a wide range of high-density
solutions at unparalleled system performance. The Delta39K
family is designed to combine the high speed, predictable
timing, and ease of use of CPLDs with the high densities and
low power of FPGAs. With devices ranging from 30,000 to
200,000 usable gates, the family features devices ten times
the size of previously available CPLDs. Even at these large
densities, the Delta39K family is fast enough to implement a
fully synthesizable 64-bit, 66-MHz PCI core.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H and V) routing
channels. Each LBC features eight individual Logic Blocks
(LB) and two cluster memory blocks. Adjacent to each LBC is
a channel memory block, which can be accessed directly from
the I/O pins. Both types of memory blocks are highly config-
urable and can be cascaded in width and depth. See Figure 1
for a block diagram of the Delta39K architecture.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
4
GCLK[3:0]
4
Channel
RAM
4
GCLK[3:0]
4
GCLK[3:0]
4
GCLK[3:0] PLL and Clock MUX
GCTL[3:0]
I/O Bank 6
I/O Bank 7
I/O Bank 3
I/O Bank 2
I/
O
B
a
n
k
4
I/O
Ba
n
k
5
I/O
Ba
n
k
1
I/O
Ba
n
k
0
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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CY3950Z208-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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