參數(shù)資料
型號: CY7C106B-25VC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 256K x 4 Static RAM
中文描述: 256K X 4 STANDARD SRAM, 25 ns, PDSO28
封裝: 0.400 INCH, SOJ-28
文件頁數(shù): 7/10頁
文件大?。?/td> 161K
代理商: CY7C106B-25VC
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. **
Page 6 of 10
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[10]
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
Data Retention Current
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
250
A
tCDR
[4]
Chip Deselect to Data Retention Time
0
ns
tR
[4]
Operation Recovery Time
200
s
Data Retention Waveform
4.5V
CE
VCC
tCDR
VDR > 2V
DATA RETENTION MODE
tR
C106B–5
Switching Waveforms
Read Cycle No.1[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10. No input may exceed VCC +0.5V.
11. Device is continuously selected, OE and CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
1
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
C106B–6
C106B–7
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
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