參數(shù)資料
型號(hào): CY7C1334
廠商: Cypress Semiconductor Corp.
英文描述: 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM)
中文描述: 64Kx32流過(guò)式的SRAM架構(gòu)的總線延遲(帶總線延遲結(jié)構(gòu)的64Kx32流通式的SRAM)
文件頁(yè)數(shù): 10/11頁(yè)
文件大?。?/td> 184K
代理商: CY7C1334
CY7C1334
10
Switching Waveforms
(continued)
ADV/LD
CLK
ADDRESS
CE
1a
Data-
In/Out
t
CYC
t
CH
t
CL
t
ALS
t
ALH
RA1
t
AH
t
AS
t
CES
t
CEH
t
CO
Q1
Out
= DON
T CARE
= UNDEFINED
The combination of WE & BWS
[3:0]
define a write cycle (see Write Cycle Description table).
CE is the combination of CE
1
, CE
2
, and CE
3
. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS
[3:0]
input signals.
Burst order determined by the state of the Mode input. CEN held LOW. OE held LOW.
B
B
t
CLZ
t
DOH
Device
originally
deselected
WA2
Q1+1
Out
Q1+2
Out
Q1+3
Out
RA3
t
CLZ
t
CHZ
D2+1
In
D2+2
In
D2+3
In
D2
In
t
CO
Q3
Out
t
DS
t
DH
B
B
B
B
B
B
B
B
B
Burst Sequences
WS
[3:0]
t
WS
t
WH
WE
t
WS
t
WH
相關(guān)PDF資料
PDF描述
CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM)
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CY7C1338G-117AXI 4-Mbit (128K x 32) Flow-Through Sync SRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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CY7C1334H-166AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 64Kx32 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C133-55JC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 55ns 68-Pin PLCC