- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379064 > CY7C1355C_06 (Cypress Semiconductor Corp.) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1355C_06 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流量，通過與建筑的SRAM總線延遲⑩ |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 456K |
| 代理商： | CY7C1355C_06 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. *E
Page 9 of 28
precaution, DQs and DQP
X
are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the Chip Enables (CE
1
, CE
2
, and CE
3
) and
WE inputs are ignored and the burst counter is incremented.
The correct BW
X
inputs must be driven in each cycle of the
burst write, in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
. .
ZZ Mode Electrical Characteristics
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
50
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
None
None
None
None
External
Next
External
Next
External
Next
CE
1
CE
2
CE
3
ZZ
H
X
X
X
X
L
X
X
L
H
X
X
L
H
X
X
L
H
X
X
ADV/LD WE BW
X
OE CEN CLK
L
X
X
L
X
X
L
X
X
H
X
X
L
H
X
H
X
X
L
H
X
H
X
X
L
L
L
H
X
L
DQ
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
X
H
X
X
L
X
L
X
L
X
L
L
L
L
L
L
L
L
L
L
X
X
X
X
L
L
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L->H
L->H
L->H
L->H
L->H Data Out (Q)
L->H Data Out (Q)
L->H
Tri-State
L->H
Tri-State
L->H
Data In (D)
L->H
Data In (D)
Tri-State
Tri-State
Tri-State
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP
X
= Tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
X
= data when OE is active.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1355C-100AXC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1355C-100AXI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1357C-100BGXC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1357C-100BGXI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1357C-100BZC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1355C-100AXC | 功能描述:IC SRAM 9MBIT 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:NoBL™ 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1355C-100AXCT | 功能描述:IC SRAM 9MBIT 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:NoBL™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1355C-100AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1355C-100BGC | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1355C-100BGCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。