參數(shù)資料
型號: CY7C1355C-100BGXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
中文描述: 256K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
文件頁數(shù): 15/28頁
文件大?。?/td> 456K
代理商: CY7C1355C-100BGXC
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. *E
Page 15 of 28
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
69
69
Bit Size (x18)
3
1
32
69
69
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料
PDF描述
CY7C1355C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C_06 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C-100AXC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C-100AXI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1357C-100BGXC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
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