參數(shù)資料
型號: CY7C1355C-100BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
中文描述: 256K X 36 ZBT SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 14/28頁
文件大?。?/td> 456K
代理商: CY7C1355C-100BZXI
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. *E
Page 14 of 28
3.3V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics
And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 3.3V ± 0.165V unless
otherwise noted)
[12]
Parameter
V
OH1
Description
Output HIGH Voltage
Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
V
OH2
Output HIGH Voltage
I
OH
= –100 μA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 8.0 mA
I
OL
= 100 μA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
V
IH
Input HIGH Voltage
2.0
1.7
–0.5
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.7
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
CY7C1355C
(256Kx36)
010
01010
001001
100110
00000110100
1
CY7C1357C
(512Kx18)
010
01010
001001
010110
00000110100
1
Description
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Describes the version number
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Note:
12.All voltages referenced to V
SS
(GND).
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相關(guān)PDF資料
PDF描述
CY7C1355C-133AXC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C-133AXI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C-133BGXC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C-133BGXI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
CY7C1355C-133BZXC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture
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