參數(shù)資料
型號: CY7C1370D-250AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
中文描述: 512K X 36 ZBT SRAM, 2.6 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁數(shù): 13/30頁
文件大?。?/td> 344K
代理商: CY7C1370D-250AXC
PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 13 of 30
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
[9, 10]
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
9. t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
10.Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1 ns.
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
ns
20
25
25
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
5
ns
ns
0
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
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