參數(shù)資料
型號: CY7C1372D-200AXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
中文描述: 1M X 18 ZBT SRAM, 3 ns, PQFP100
封裝: (14 X 20 X 1.4) MM, LEAD FREE, PLASTIC, TQFP-100
文件頁數(shù): 23/30頁
文件大小: 344K
代理商: CY7C1372D-200AXI
PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 23 of 30
Switching Waveforms
Read/Write/Timing
[25, 26, 27]
Notes:
25.For this waveform ZZ is tied LOW.
26.When CE is LOW, CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH,CE
is HIGH or CE
is LOW or CE
is HIGH.
27.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW
x
ADV/LD
t
AH
t
AS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1)
D(A2)
D(A5)
Q(A4)
Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE
UNDEFINED
Q(A6)
Q(A4+1)
相關(guān)PDF資料
PDF描述
CY7C1372D-200BGC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200BGI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200BZC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200BZI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-225AXC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
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CY7C1372DV25-167BGI 制造商:Cypress Semiconductor 功能描述:
CY7C1372DV25-167BZC 制造商:Cypress Semiconductor 功能描述:
CY7C1372DV25-167BZXC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: