參數(shù)資料
型號: CY7C1381DV25-100AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述: 512K X 36 CACHE SRAM, 8.5 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
文件頁數(shù): 28/28頁
文件大?。?/td> 952K
代理商: CY7C1381DV25-100AXC
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E
Page 28 of 28
Document History Page
Document Title: CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/CY7C1383FV25, 18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM
Document Number: 38-05547
Orig. of
Change
**
254518
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117Mhz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed
Θ
JA
and
Θ
JC
for TQFP Package
from 31 and 6
°
C/W to 28.66 and
4.08
°
C/W respectively
Changed
Θ
JA
and
Θ
Jc
or BGA Package
from 45 and 7
°
C/W to 23.8 and 6.2
°
C/W respectively
Changed
Θ
JA
and
Θ
Jc
for FBGA Package
from 46 and 3
°
C/W to 20.7 and
4.0
°
C/W respectively
Modified V
OL,
V
OH
test conditions
Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
*C
416321
See ECN
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 17
Changed the I
X
current values of MODE on page # 18 from –5
μ
A and 30
μ
A
to –30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 18 from –30
μ
A and 5
μ
A
to –5
μ
A and 30
μ
A
Changed V
IH
< V
DD
to V
IH
< V
DD
on page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
*D
475009
See ECN
VKN
Converted from Preliminary to Final.
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
*E
793579
See ECN
VKN
Added Part numbers CY7C1381FV25 and CY7C1383FV25
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
REV.
ECN NO.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1381DV25-100AXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-100BZC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-100BZI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-100BZXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-100BZXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
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參數(shù)描述
CY7C1381DV25-133AXC 制造商:Cypress Semiconductor 功能描述:
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