參數(shù)資料
型號(hào)： CY7C1381DV25-100BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述： 512K X 36 CACHE SRAM, 8.5 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 952K
代理商： CY7C1381DV25-100BZC
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E
Page 17 of 28
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND ....... –0.3V to +3.6V
Supply Voltage on V
DDQ
Relative to GND......–0.3V to +V
DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage ...................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
2.5V
±
5% 2.5V – 5%
to
V
DD
Electrical Characteristics
Over the Operating Range
[16, 17]
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
Description
Power Supply Voltage
IO Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[16]
Input LOW Voltage
[16]
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = V
SS
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
V
DD
Unit
V
V
V
V
V
V
μ
A
for 2.5V IO
for 2.5V IO, I
OH
= –1.0 mA
for 2.5V IO, I
OL
= 1.0 mA
for 2.5V IO
for 2.5V IO
GND
≤
V
I
≤
V
DDQ
0.4
1.7
–0.3
–5
V
DD
+ 0.3V
0.7
5
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
Input = V
DD
Input = V
SS
Input = V
DD
5
Input Current of ZZ
–5
30
5
210
175
140
120
I
OZ
I
DD
Output Leakage Current GND
≤
V
I
≤
V
DD,
Output Disabled
V
DD
Operating Supply
Current
f = f
MAX
= 1/t
CYC
–5
V
DD
= Max., I
OUT
= 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
I
SB1
Automatic CE
Power Down
Current—TTL Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = f
MAX,
inputs switching
Max. V
DD
, Device Deselected,
V
IN
≥
V
DD
– 0.3V or V
IN
≤
0.3V,
f = 0, inputs static
Max. V
DD
, Device Deselected,
V
IN
≥
V
DDQ
– 0.3V or V
IN
≤
0.3V,
f = f
MAX
, inputs switching
Max. V
DD
, Device Deselected,
V
IN
≥
V
DD
– 0.3V or V
IN
≤
0.3V,
f = 0, inputs static
I
SB2
All speeds
70
mA
I
SB3
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
130
110
mA
mA
I
SB4
All speeds
80
mA
Notes
16.Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC) > –2V (Pulse width less than t
CYC
/2).
17.T
power up
: assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1381DV25-100BZI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-100BZXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-100BZXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-133AXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25-133AXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1381DV25-133AXC 制造商:Cypress Semiconductor 功能描述:
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CY7C1381F-133BGCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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CY7C1381XC 制造商:Cypress Semiconductor 功能描述:
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