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參數(shù)資料
| 型號： | CY7C1381DV25-100BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 8.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大小： | 952K |
| 代理商： | CY7C1381DV25-100BZXC |
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18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Cypress Semiconductor Corporation
Document #: 38-05547 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised Feburary 14, 2007
Features
Supports 133 MHz bus operations
512K x 36/1M x 18 common IO
2.5V core power supply (V
DD
)
2.5V IO supply (V
DDQ
)
Fast clock-to-output times, 6.5 ns (133 MHz version)
Provides high-performance 2-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
CY7C1381DV25/CY7C1383DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1381FV25/CY7C1383FV25 available in Pb-free and
non Pb-free 119-ball BGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option
Functional Description
[1]
The
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in
a burst and increments the address automatically for the rest
of the burst access. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE
1
), depth expansion
chip enables (CE
2
and
CE
3 [2]
), burst control inputs (ADSC,
ADSP, and ADV), write enables (BW
x
, and BWE), and global
write (GW). Asynchronous inputs include the output enable
(OE) and the ZZ pin.
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
The
CY7C1383FV25 allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
The
CY7C1383FV25 operates from a +2.5V core power supply
while all outputs also operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
Selection Guide
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3,
CE
2
are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1381DV25-100BZXI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381DV25-133AXC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381DV25-133AXI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381DV25-133BZC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381DV25-133BZXC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1381DV25-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381F-133BGC | 功能描述:靜態(tài)隨機存取存儲器 512Kx36 3.3V Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381F-133BGCT | 功能描述:靜態(tài)隨機存取存儲器 512Kx36 3.3V Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381S-133AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1381S-133AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381XC | 制造商:Cypress Semiconductor 功能描述: |
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