參數(shù)資料
型號(hào)： CY7C1381FV25-100BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述： 512K X 36 CACHE SRAM, 8.5 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
文件頁數(shù)： 19/28頁
文件大小： 952K
代理商： CY7C1381FV25-100BGI
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E
Page 19 of 28
Switching Characteristics
Over the Operating Range
[19, 20]
Parameter
Description
133 MHz
100 MHz
Unit
Min.
Max.
Min.
Max.
t
POWER
Clock
V
DD
(Typical) to the first Access
[21]
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
7.5
10
ns
Clock HIGH
2.1
2.5
ns
Clock LOW
2.1
2.5
ns
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
Data Output Valid After CLK Rise
6.5
8.5
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[22, 23, 24]
Clock to High-Z
[22, 23, 24]
2.0
2.0
ns
2.0
2.0
ns
0
4.0
0
5.0
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[22, 23, 24]
OE HIGH to Output High-Z
[22, 23, 24]
3.2
3.8
ns
0
0
ns
4.0
5.0
ns
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
Address Setup Before CLK Rise
1.5
1.5
ns
ADSP, ADSC Setup Before CLK Rise
1.5
1.5
ns
ADV Setup Before CLK Rise
1.5
1.5
ns
GW, BWE, BW
[A:D]
Setup Before CLK Rise
Data Input Setup Before CLK Rise
1.5
1.5
ns
1.5
1.5
ns
Chip Enable Setup
1.5
1.5
ns
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
Address Hold After CLK Rise
0.5
0.5
ns
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
GW, BWE, BW
[A:D]
Hold After CLK Rise
ADV Hold After CLK Rise
0.5
0.5
ns
0.5
0.5
ns
Data Input Hold After CLK Rise
0.5
0.5
ns
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes
19.Timing reference level is 1.25V.
20.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a read or write operation
can be initiated.
22.t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
23.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
24.This parameter is sampled and not 100% tested.
[+] Feedback
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