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參數(shù)資料
| 型號： | CY7C1381FV25-100BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 952K |
| 代理商： | CY7C1381FV25-100BGI |
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E
Page 9 of 28
Truth Table
[4, 5, 6, 7, 8]
Cycle Description
Address
Used
None
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
H
X
X
L
X
L
X
X
X
L-H Tri-State
None
L
L
X
L
L
X
X
X
X
L-H Tri-State
None
L
X
H
L
L
X
X
X
X
L-H Tri-State
None
L
L
X
L
H
L
X
X
X
L-H Tri-State
None
X
X
X
L
H
L
X
X
X
L-H Tri-State
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
X
Tri-State
L-H Q
L-H Tri-State
L-H D
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
L-H D
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
L-H D
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1381FV25-100BGXC | Replacement for Intersil part number 131684. Buy from authorized manufacturer Rochester Electronics. |
| CY7C1381FV25-100BGXI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381FV25-133BGC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381FV25-133BGI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381FV25-133BGXC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
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