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參數(shù)資料
| 型號(hào)： | CY7C1383FV25-100BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 |
| 文件頁(yè)數(shù)： | 8/28頁(yè) |
| 文件大?。?/td> | 952K |
| 代理商： | CY7C1383FV25-100BGXI |
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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E
Page 8 of 28
and the IOs must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3 [2]
are all
asserted active, (2) ADSC is asserted LOW, (3) ADSP is
deserted HIGH, and (4) the write input signals (GW, BWE, and
BW
X
) indicate a write access. ADSC is ignored if ADSP is
active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core. The information presented to DQ
X
will be
written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The
CY7C1383FV25 provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
[1:0]
,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
1
, CE
2
, CE
3 [2]
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
A1: A0
00
01
10
11
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
A1: A0
00
01
01
10
10
11
11
00
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
01
00
11
10
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
80
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
[+] Feedback
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