參數(shù)資料
型號(hào)： CY7C1471V25-133BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述： 2M X 36 ZBT SRAM, 6.5 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件頁(yè)數(shù)： 23/30頁(yè)
文件大?。?/td> 373K
代理商： CY7C1471V25-133BZC
PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 23 of 30
Switching Characteristics
Over the Operating Range
[20, 21]
Parameter
t
POWER‘
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Notes:
16.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a read or write operation
can be initiated.
17.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
18.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
19.This parameter is sampled and not 100% tested.
20.Timing reference level is 1.25V when V
= 2.5V and is 0.9V when V
DDQ
= 1.8V.
21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Description
133 MHz
Min.
1
100 MHz
Min.
1
Unit
ms
Max.
Max.
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[17, 18, 19]
Clock to High-Z
[17, 18, 19]
OE LOW to Output Valid
OE LOW to Output Low-Z
[17, 18, 19]
OE HIGH to Output High-Z
[17, 18, 19]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
2.5
3.0
2.5
3.0
3.8
3.0
4.5
3.8
0
0
3.0
4.0
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BW
X
Set-up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BW
X
Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料
PDF描述
CY7C1473V25-100AXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V25-100BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V25-100BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V25-100BGC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V25-100BGXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1471V33-100AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk
CY7C1471V33-100AXI 制造商:Cypress Semiconductor 功能描述:
CY7C1471V33-117AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1471V33-117AXCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk
CY7C1471V33-133AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 6.5NS 100TQFP - Bulk
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