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參數(shù)資料
| 型號： | CY7C1471V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 72兆位（2米x 36/4M x 18/1M × 72）流體系結構，通過與總線延遲靜態(tài)存儲器 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 373K |
| 代理商： | CY7C1471V25 |
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PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 17 of 30
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
71
-
Bit Size (x18)
3
1
32
52
-
Bit Size (x72)
3
1
32
-
110
Instruction
Bypass
ID
Boundary Scan Order-165FBGA
Boundary Scan Order- 209BGA
Identification Codes
Instruction
Code
000
Description
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1
compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation. This instruction does not implement 1149.1
preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1475V33-133BGXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V25-100AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V25-133BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V25-133BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1471V25-100AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1471V25-100BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1471V25-133AXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (2Mx36) 2.5v 133MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1471V25-133AXCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 6.5NS 100TQFP - Bulk |
| CY7C1471V25-133AXCT | 功能描述:靜態(tài)隨機存取存儲器 2Mx36 2.5V NoBL FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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