參數(shù)資料
型號： CY7C1471V33-133BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述： 2M X 36 ZBT SRAM, 6.5 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件頁數(shù)： 25/30頁
文件大?。?/td> 373K
代理商： CY7C1471V33-133BZC
PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 25 of 30
NOP, STALL and DESELECT Cycles
[22, 23, 25]
1
Note:
25.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Switching Waveforms
(continued)
WRITE
D(A1)
2
3
4
5
6
7
8
9
CLK
tCYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BW
X
ADV/LD
tAH
tAS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
tDH
tDS
DQ
COMMAND
tCLZ
D(A1)
D(A2)
Q(A4)
Q(A3)
D(A2+1)
tDOH
tCHZ
tCDV
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE
UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)
Q(A6)
相關(guān)PDF資料
PDF描述
CY7C1475V33-100BGC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V33-100BGXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1475V33-133BGC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V33-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V33-100AXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1471V33-133BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 6.5NS 165FBGA - Bulk
CY7C1471V33-133BZI 制造商:Cypress Semiconductor 功能描述:
CY7C1471XC 制造商:Cypress Semiconductor 功能描述:
CY7C14722AC 制造商:Cypress Semiconductor 功能描述:
CY7C14722BC 制造商:Cypress Semiconductor 功能描述:
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