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參數(shù)資料
| 型號(hào)： | CY7C1473V33-100BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 4M X 18 ZBT SRAM, 8.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 375K |
| 代理商： | CY7C1473V33-100BZXC |
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PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *E
Page 8 of 29
Pin Definitions
Name
A
0
, A
1
, A
I/O
Input-
Description
Synchronous
Input-
Synchronous
Address Inputs used to select one of the address locations
. Sampled at the rising edge
of the CLK. A
[1:0]
are fed to the two-bit burst counter.
Byte Write Inputs, active LOW
. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
BW
A
, BW
B
, BW
C
,
BW
D
, BW
E
, BW
F
,
BW
G
, BW
H
WE
Input-
Synchronous
Input-
Synchronous
Write Enable Input, active LOW
. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input
. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected,
ADV/LD should be driven LOW in order to load a new address.
Clock Input
. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
2
, and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and
CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW
. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW
. When asserted LOW the Clock signal is recognized by
the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
ZZ “Sleep” Input
. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected
to Vss or left floating.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ
s
and DQP
X
are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to DQ
s
.
During
write sequences, DQP
X
is controlled by BW
X
correspondingly.
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V
DD
or left floating selects
interleaved burst sequence.
Power supply inputs to the core of the device
.
I/O Power Supply
Power supply for the I/O circuitry
.
Ground
Ground for the device
.
JTAG serial output
Synchronous
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
JTAG serial input
Synchronous
is not being utilized, this pin can be left floating or connected to V
DD
through a pull up
resistor. This pin is not available on TQFP packages.
ADV/LD
CLK
Input-
Clock
Input-
CE
1
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
2
CE
3
OE
CEN
Input-
Synchronous
ZZ
Input-
Asynchronous
DQ
s
I/O-
Synchronous
DQP
X
I/O-
Synchronous
Input Strap Pin
MODE
V
DD
V
DDQ
V
SS
TDO
Power Supply
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of TCK. If the
TDI
Serial data-In to the JTAG circuit
. Sampled on the rising edge of TCK. If the JTAG feature
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1473V33-133AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V33-133BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V33-100BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V33-100BZXC | LME Series; Mounting Style: Direct mount; Functions: Continuous light; Light Type: LED; Rated Voltage: 24V AC/DC; Style: 2 - light; Color: Red, Green (other color combo avail); Diameter: 60; Applicable Model: LME |
| CY7C1471V33-133BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
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