參數(shù)資料
型號(hào): CY7C1475V25-133BGXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述: 1M X 72 ZBT SRAM, 6.5 ns, PBGA209
封裝: 14 X 22 MM, 1.76 MM HEIGHT, LEAD FREE, FBGA-209
文件頁數(shù): 22/30頁
文件大?。?/td> 373K
代理商: CY7C1475V25-133BGXC
PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 22 of 30
Thermal Resistance
[15]
Parameter
Θ
JA
Description
Test Conditions
165 fBGA
Package
16.3
209 BGA
Package
15.2
TQFP
Package
24.63
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
Θ
JC
2.1
1.7
2.28
°
C/W
Capacitance
[15]
Parameter
Description
Test Conditions
TQFP
Max.
209-BGA
Max.
165-fBGA
Max.
Unit
C
ADDRESS
Address Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 2.5V
V
DDQ
= 2.5V
6
6
6
pF
C
DATA
Data Input Capacitance
5
5
5
pF
C
CTRL
Control Input Capacitance
8
8
8
pF
C
CLK
Clock Input Capacitance
6
6
6
pF
C
I/O
Input/Output Capacitance
5
5
5
pF
AC Test Loads and Waveforms
Note:
15.Tested initially and after any design or process change that may affect these parameters
OUTPUT
R = 1667
R = 1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
1 ns
1 ns
(c)
2.5V I/O Test Load
OUTPUT
R = 14K
R = 14K
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 0.9V
1.8V
ALL INPUT PULSES
V
DDQ
- 0.2
0.2
90%
10%
90%
10%
1 ns
1 ns
(c)
1.8V I/O Test Load
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