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參數(shù)資料
| 型號(hào)： | CY7C1481V33-150AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| 中文描述： | 2M X 36 STANDARD SRAM, 5.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 9/30頁(yè) |
| 文件大?。?/td> | 638K |
| 代理商： | CY7C1481V33-150AC |
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PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 9 of 30
Functional Description
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip enable (CE
1
, CE
2
, CE
3
on TQFP, CE
1
on BGA) asserted
active, and (3) the write signals (GW, BWE) are all deasserted
HIGH. ADSP is ignored if CE
1
is HIGH. The address presented
to the address inputs is stored into the address advancement
logic and the Address Register while being presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs a maximum to t
CDV
after clock rise. ADSP is ignored if CE
1
is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
Chip Enable asserted active. The address presented is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The write signals (GW,
BWE, and BWx) and ADV inputs are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched
and
written
into
CY7C1481V33/CY7C1483V33/CY7C1487V33 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BW
a,b,c,d,e,f,g,h
for CY7C1487V33,
BW
a,b,c,d
for CY7C1481V33 and BW
a,b
for CY7C1483V33)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered.
All I/Os are three-stated during a byte write.
Because the CY7C1481V33/CY7C1483V33/CY7C1487V33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQx
inputs.
Doing so will three-state the output drivers. As a safety
the
device.
The
precaution, DQx are automatically three-stated whenever a
write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) Chip Enable (CE
1
, CE
2
, CE
3
on TQFP,
CE
1
on BGA) asserted active, and (4) the appropriate combi-
nation of the write inputs (GW, BWE, and BW
x
) are asserted
active to conduct a write to the desired byte(s). ADSC is
ignored if ADSP is active LOW.
The address presented to A
[17:0]
is loaded into the address
register and the address advancement logic while being
delivered to the RAM core. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQx is written into the corresponding address location in
the RAM core. If a byte write is conducted, only the selected
bytes are written. Bytes not selected during a byte write
operation will remain unaltered. All I/Os are three-stated
during
a
byte
write
because
CY7C1483V33/CY7C1487V33 is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before
presenting data to the DQx inputs. Doing so will three-state the
output drivers. As a safety precaution, DQx are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
the
CY7C1481V33/
Burst Sequences
The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides
a two-bit wraparound counter, fed by A
[1:0]
, that implements
either an interleaved or linear burst sequence. to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Cycle Descriptions
[1, 2, 3, 4]
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Add. Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
ZZ
0
0
0
0
0
0
0
0
0
0
0
0
CE
3
X
1
X
1
X
0
0
X
X
X
X
X
CE
2
X
X
0
X
0
1
1
X
X
X
X
X
CE
1
1
0
0
0
0
0
0
X
X
1
1
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
0
1
OE
X
X
X
X
X
X
X
1
0
1
0
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Notes:
1.
2.
3.
4.
X =
“
Don't Care.
”
1 = HIGH, 0 = LOW.
Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
CE
1
, CE
2
, and CE
3
are available only in the TQFP package. BGA package has a single chip select CE
1
.
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