參數(shù)資料
型號: CY7C1481V33
廠商: Cypress Semiconductor Corp.
元件分類: DRAM
英文描述: 2M x 36/4M x 18/1M x 72 Flow-through SRAM
中文描述: 2米x 36/4M x 18/1M × 72流通過的SRAM
文件頁數(shù): 15/30頁
文件大小: 638K
代理商: CY7C1481V33
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 15 of 30
TAP Electrical Characteristics
Over the Operating Range
[7, 8]
TAP Controller Block Diagram
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
.
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Test Conditions
I
OH
=
4.0 mA
I
OH
=
100
μ
A
I
OL
= 8.0 mA
I
OL
= 100
μ
A
Min.
2.4
3.0
Max.
Unit
V
V
V
V
V
V
μ
A
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
0.4
0.2
1.8
0.5
5
V
DD
+
0.3
0.8
5
GND
V
I
V
DDQ
TAP AC Switching Characteristics
Over the Operating Range
[9, 10]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Notes:
7.
All Voltage referenced to Ground.
8.
Overshoot: V
(AC)<V
+1.5V for t<t
/2, Undershoot: V
(AC)<0.5V for t<t
/2, Power-up: V
<2.6V and V
DD
<2.4V and V
DDQ
<1.4V for t<200 ms.
9.
t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
Description
Min.
100
Max
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
10
40
40
相關(guān)PDF資料
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CY7C1481V33-100AC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1481V33-100BGC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
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