參數(shù)資料
型號： CY7C1482V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM(72-Mb (2M x 36/4M x 18/1M x 72) 管道式同步SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流水線同步靜態(tài)存儲器（72 - MB的（2米x 36/4M x 18/1M × 72）管道式同步靜態(tài)存儲器）
文件頁數(shù)： 15/32頁
文件大?。?/td> 1235K
代理商： CY7C1482V33
CY7C1480V33
CY7C1482V33
CY7C1486V33
Document #: 38-05283 Rev. *H
Page 15 of 32
3.3V TAP AC Test Conditions
Input pulse levels............................................... .V
SS
to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
3.3V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
50
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; VDD = 3.135 to 3.6V unless otherwise noted)
[11]
Parameter
V
OH1
Description
Output HIGH Voltage I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
Output HIGH Voltage I
OH
= –100 μA
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
V
OH2
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
CY7C1480V33
(2M x36)
000
01011
000000
100100
00000110100
CY7C1482V33
(4M x 18)
000
01011
000000
010100
00000110100
CY7C1486V33
(1M x72)
000
01011
000000
110100
00000110100 Enables unique identification of SRAM
vendor
1
Indicates the presence of an ID register
Description
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
ID Register Presence Indicator (0)
1
1
Notes
11. All voltages referenced to V
SS
(GND).
相關(guān)PDF資料
PDF描述
CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM(72-Mb (2M x 36/4M x 18/1M x 72) 管道式同步SRAM)
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