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參數(shù)資料
| 型號： | CY7C1483V33-100BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| 中文描述： | 4M X 18 STANDARD SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 638K |
| 代理商： | CY7C1483V33-100BGC |
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PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 8 of 30
CLK
Input-
Clock
Input-
Clock Input
. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device.(TQFP Only)
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and
CE
2
to select/deselect the device.(TQFP Only)
Output Enable, asynchronous input, active LOW
. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK
. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK
. When asserted LOW,
A is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK
. When asserted LOW,
A
[x:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP is recognized.
Selects Burst Order
. When tied to GND selects linear burst sequence. When tied to V
DDQ
or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation.
ZZ
“
sleep
”
Input
. This active HIGH input places the device in a non-time critical
“
sleep
”
condition with data integrity preserved.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx
and DPx
are placed in a three-state condition. DQ a,b,c,d,e,f,g and h are 8 bits wide. DP
a,b,c,d,e,f,g and h are 1 bit wide.
CE
1
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
2
CE
3
OE
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
MODE
Input-
Static
ZZ
Input-
Asynchronous
I/O-
Synchronous
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
DQe, DPe
DQf, DPf
DQg, DPg
DQh, DPh
TDO
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Test Mode Select
Synchronous
JTAG serial clock
Serial clock to the JTAG circuit
. (BGA Only)
Power Supply
Power supply inputs to the core of the device
. Should be connected to 3.3V
–
5% +5% power
supply.
Ground
Ground for the core of the device
. Should be connected to ground of the system.
I/O Power Supply
Power supply for the I/O circuitry
. Should be connected to a 2.375V(min.) to V
DD
(max.)
I/O Ground
Ground for the I/O circuitry
. Should be connected to ground of the system.
–
NC. This pin is reserved for expansion to 144Mb.
–
No connects
.
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of TCK. (BGA Only)
TDI
Serial data-In to the JTAG circuit
. Sampled on the rising edge of TCK.(BGA Only)
TMS
This pin controls the Test Access Port state machine
. Sampled on the rising edge of TCK.
(BGA Only)
TCK
V
DD
V
SS
V
DDQ
V
SSQ
144M
NC
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1483V33-100BZC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-117AC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-117BGC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-117BZC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-133AC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C148-45DC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 1Kx4, 18 Pin, Ceramic, DIP |
| CY7C148-45PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1484BV25-250AXI | 制造商:Cypress Semiconductor 功能描述:SYNC - Trays 制造商:Cypress Semiconductor 功能描述:IC SRAM 72MBIT 250MHZ 100TQFP 制造商:Cypress Semiconductor 功能描述:TRAY / Sync SRAMs |
| CY7C1484BV33-250BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1484BV33-250BZXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (2Mx36) 3.3v 250MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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