參數(shù)資料
型號: CY7C1483V33-117BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2M x 36/4M x 18/1M x 72 Flow-through SRAM
中文描述: 4M X 18 STANDARD SRAM, 7.5 ns, PBGA165
封裝: 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
文件頁數(shù): 24/30頁
文件大小: 638K
代理商: CY7C1483V33-117BZC
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 24 of 30
Notes:
22. Device originally deselected.
23. CE is the combination of CE
2
and CE
3
. All chip selects need to be active in order to select the device.
Switching Waveforms
(continued)
Read/Write Timing
In/Out
A
t
AH
t
AS
= DON
T CARE
= UNDEFINED
WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
CE is the combination of CE
2
and CE
3
. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
t
CLZ
t
CHZ
t
DOH
CLK
ADD
WE
CE
1
Data
B
C
D
ADSP
ADSC
ADV
CE
OE
Q(A)
Q(B)
Q
(B+1)
Q
(B+2)
Q
(B+3)
Q(B)
D(C)
D
(C+1)
D
(C+2)
D
(C+3)
Q(D)
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADS
t
ADH
t
ADVH
t
ADVS
t
CEH
t
CEH
t
CES
t
CES
t
WEH
t
WES
t
CDV
Device originally
deselected
ADSP ignored
with CE
1
HIGH
t
EOHZ
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