參數(shù)資料
型號(hào)： CY7C1483V33-133AXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
中文描述： 4M X 18 CACHE SRAM, 6.5 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
文件頁(yè)數(shù)： 8/30頁(yè)
文件大?。?/td> 998K
代理商： CY7C1483V33-133AXI
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *H
Page 8 of 30
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
CDV
) is 6.5 ns (133-MHz device).
The CY7C1481V33/CY7C1483V33/CY7C1487V33 supports
secondary cache in systems using either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486 processors. The linear burst sequence is
suited for processors that use a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide easy bank
selection and output tri-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data is
available at the data outputs a maximum to t
CDV
after clock
rise. ADSP is ignored if CE
1
is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, CE
3
are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW
X
) are ignored during this first clock
cycle. If the write inputs are asserted active (see
“Truth Table
for Read/Write” on page 11
for appropriate states that indicate
a write) on the next clock rise, the appropriate data is latched
and written into the device. Byte writes are supported. All IOs
are tri-stated during a byte write. Because this is a common IO
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated before the presentation of data
to DQ
s
. As a safety precaution, the data lines are tri-stated
after a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
s
will be written
into the specified address location. Byte writes are supported.
V
DD
V
DDQ
V
SS
V
SSQ[2}
TDO
Power Supply
Power supply inputs to the core of the device
.
IO Power Supply
Power supply for the IO circuitry
.
Ground
Ground for the core of the device
.
I/O Ground
Ground for the IO circuitry
.
JTAG Serial
Output
Synchronous
Serial Data-Out to the JTAG Circuit
. Delivers data on the negative edge of TCK. If
the JTAG feature is not used, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG Serial Input
Synchronous
Serial Data-In to the JTAG Circuit
. Sampled on the rising edge of TCK. If the JTAG
feature is not used, this pin can be left floating or connected to V
DD
through a pull up
resistor. This pin is not available on TQFP packages.
TMS
JTAG Serial Input
Synchronous
Serial Data-In to the JTAG Circuit
. Sampled on the rising edge of TCK. If the JTAG
feature is not used, this pin can be disconnected or connected to V
DD
. This pin is not
available on TQFP packages.
TCK
JTAG Clock
Clock Input to the JTAG Circuit
. If the JTAG feature is not used, this pin must be
connected to V
SS
. This pin is not available on TQFP packages.
No Connects
. Not internally connected to the die. 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
NC
-
Pin Definitions
(continued)
Pin Name
IO
Description
Note
2. Applicable for TQFP package. For BGA package V
SS
serves as ground for the core and the IO circuitry.
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1483V33-133BZI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1483V33-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1483V33-133BZXI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1487V33-100BGI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
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