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參數(shù)資料
| 型號： | CY7C1484V25-167AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2M X 36 CACHE SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 906K |
| 代理商： | CY7C1484V25-167AXI |
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CY7C1484V25
CY7C1485V25
Document #: 38-05286 Rev. *H
Page 26 of 26
Document History Page
Document Title: CY7C1484V25/CY7C1485V25 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
Document Number: 38-05286
Issue
Date
Change
**
114672
08/21/02
PKS
New Data Sheet
*A
118285
01/20/03
HGK
Changed tCO from 2.4 to 2.6 ns for 250 MHz
Updated Features on package offering
Updated Ordering information
Changed Advanced Information to Preliminary
*B
233368
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz offering and included 225-MHz speed bin
Changed package outline for 165FBGA package
Removed 119-BGA package offering
*C
299511
See ECN
SYT
Removed 225-MHz offering and included 250-MHz speed bin
Changed t
CYC
from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
Changed
Θ
JA
from 16.8 to 24.63
°
C/W and
Θ
JC
from 3.3 to 2.28
°
C/W for 100
TQFP Package on Page # 16
Added lead-free information for 100-Pin TQFP and 165 FBGA Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*D
320197
See ECN
PCI
Changed typo in the part number from CY7C1484V33 and CY7C1485V33 to
CY7C1484V25 and CY7C1485V25 respectively on page numbers 2, 3, 4 and
21
*E
331513
See ECN
PCI
Unshaded 200 and 167 MHz speed bins in the AC/DC Table and Selection
Guide
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Industrial Operating Range
Modified V
OL
, V
OH
Test Conditions
Updated Ordering Information Table
*F
416221
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 16
Changed the I
X
current values of MODE on page # 16 from -5
μ
A and 30
μ
A
to -30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 16 from -30
μ
A and 5
μ
A
to -5
μ
A and 30
μ
A
Changed V
IH
< V
DD
to V
IH
< V
DD
on page # 16
Replaced Package Name column with Package Diagram in the Ordering
Information table
*G
472335
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP AC
Switching Characteristics table
Updated the Ordering Information table.
*H
1062042
See ECN VKN/KKVTMP Added footnote #2 related to V
SSQ
REV.
ECN NO.
Orig. of
Description of Change
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1484V25-167BZC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-167BZI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-167BZXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-167BZXI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-200AXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C149 WAF | 制造商:Cypress Semiconductor 功能描述: |
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| CY7C150-10DC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C150-15PC | 制造商:Rochester Electronics LLC 功能描述:4K (1K X 4)- 24 PIN 300 MIL SEPARATE I/O & RESET SRAM - Bulk |
| CY7C15025PC | 制造商:CYPRESS 功能描述:* |
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